Aerospace & Defense

High-Power Wideband L-Band Suboptimum Class-E Power Amplifier

Francisco Javier Ortega-Gonzalez, David Tena-Ramos, Moises Patiño-Gomez, Jose Manuel Pardo-Martin, and Diego Madueño-Pulido
Sep 15, 2013
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High Power Wideband L Band Suboptimum Class E Power Amplifier

I. Introduction

HIGH-EFFICIENCY power-amplification techniques provide important advantages for RF and microwave systems and circuits in general, but especially in high-power or battery-powered applications. The ability of switchmode high-efficiency power amplifiers to minimize power consumption, temperature, size, and weight of radio transmitters is well known; however, in practice, it is difficult to make use of high-efficiency switchmode amplification techniques in scenarios involving high power levels and high frequencies due to device intrinsic capacitances and switching times, package parasitics, etc. Therefore, choosing a class of operation capable of dealing with such nonidealities is crucial to achieve the benefits of high-efficiency amplification at high frequencies.

Among high-efficiency switchmode amplification classes, Class-E is known for being tolerant to transistor switching imperfections. It also requires simple load impedance profiles that can be successfully synthetized both in narrowband and wideband conditions by using simple load networks [1].

The equivalent intrinsic output capacitance (COUT) of RF and microwave transistors imposes a limit to the maximum operating frequency of a nominal Class-E amplifier (fmax) that has been investigated by several authors [2]-[7]. In practice, fmax of state-of-the-art solid-state technologies is often insufficient to cover some of the most important RF and microwave power applications. This means that using present day commercially available transistors, nominal Class-E amplifiers still cannot be built for many popular and important communications and industrial applications. Suboptimum Class-E operation can be a solution for those cases. Suboptimum Class-E retains most of the benefits of nominal Class-E beyond fmax, but tolerates higher COUT figures [8]. This means that suboptimum Class-E can operate with transistors exhibiting higher COUT than the maximum allowed for nominal Class-E operation (COUTmax) while experiencing tolerable drain efficiency degradation with respect to nominal Class-E. In addition, the load requirements for suboptimum Class-E above fmax, both at fundamental and harmonics, are similar to the load requirements for nominal Class-E. Therefore, the load networks required to build nominal Class-E amplifiers can be easily adapted to suboptimum Class-E amplifiers.

Even though suboptimum Class-E cannot provide 100% drain efficiency (ηD) above fmax, it can match the performance of other high-efficiency amplification classes such as Class-F or Class-F-1, with the advantage of requiring simpler load networks that can be designed for broadband operation. Other important aspects regarding suboptimum Class-E operation above fmax are that its inherent drain-to-source peak to average voltage ratio (VDSpeak/VDD) is lower than the VDSpeak/VDD ratio of nominal Class-E, and that its power-output capability (Pmax) is also slightly higher [9].

For all these reasons, suboptimum Class-E is a feasible alter-native for high-efficiency amplification in scenarios involving wideband operation, high power levels, high frequencies, and packaged transistors.

Gallium-nitride (GaN) transistors exhibit important advantages in switchmode amplifiers in the microwave region compared to other semiconductor technologies. The high breakdown voltage of GaN transistors is more suitable than other solid-state technologies (such as GaAs, etc.) for switchmode amplification classes, such as Class-E due to their high peak voltage requirements. Moreover, high breakdown voltage power GaN transistors typically require high load impedances, which contribute to simplify the impedance transformation networks. Moreover, these networks can be designed for low losses, thus increasing the overall efficiency of the amplifier.

In this paper, a novel wideband high-power suboptimum Class-E power amplifier for L-band is proposed. It can operate in both continuous wave (CW) and pulsed modes providing up to 180 W of output power (POUT) from 900 to 1500 MHz. It exhibits peak drain efficiency (ηDpeak) up to 85%, power gain (GP) up to 14.7 dB, and power-added efficiency (PAE) up to 81%. It covers the most important RADAR sub-bands in the L-band in all operation modes without need for adjustment. Furthermore, it does not require any gain compensation circuit when used in pulsed RADAR applications. To the best of the authors' knowledge, the proposed amplifier offers superior performance than conventional L-band amplifiers with similar output power levels.

The amplifier uses a double-cell packaged unmatched GaN HEMT (CGH4018OPP from Wolfspeed, Inc). Its load network has been designed using the load admittance synthesis technique to provide the value required by the transistor at fundamental and harmonics to operate in suboptimum Class-E over almost one octave. The load network design is based on the double reactance compensation circuit [10], [11], but it also accomplishes impedance transformation functions. The network comprises device capacitance COUT, package parasitics, and an external circuit including microstrip transmission lines and lumped capacitors.

The input network of the amplifier has been designed to ensure that the transistor switches over its entire bandwidth using constant driving power (PIN); this has been achieved by pro-viding constant and maximum voltage gain (GV) from the 50-Ω input port of the amplifier to the equivalent input capacitance of the transistor (CIN). Once again, the input network comprises device input capacitance GIN, package parasitics, and an external circuit that includes lumped components and microstrip transmission lines. The complexity of both load and input networks of the amplifier has been minimized to keep their power losses as low as possible without degrading ηD and PAE. Their simple design also contributes to ease their construction and repeatability, reducing the impact of manufacturing tolerances. This is an important practical benefit when combining several amplifiers to achieve high output power levels.

II. Amplifier Description

The amplifier uses a high-power packaged (without internal matching) GaN HEMT; this feature is crucial for the design of the amplifier, as it will be shown in the following sections that the intrinsic capacitances of the device and the package poro-sities are relevant parts of the load and input networks. Three major parts and subnetworks can be distinguished in this amplifier, as shown in Fig. 1: transistor (including die and package), load network, and input network. Sections II-A~II-H describe the different subnetworks shown in Fig. 1.

Fig. 1. Parts and subnetworks of the amplifier.
Fig. 2. CGHH40180PP fmax versus POUT.

A. Transistor
The high breakdown voltage of the transistor used in this amplifier (VBR = 120 V) suggests safe operation for this de-vice in nominal Class-E at power supply voltages (VDD) as high as 28 V. However, prior to any further considerations, it is necessary to determine if the operating frequency of the amplifier is above or below the fmax, allowed by the transistor. fmax can be calculated from the transistor COUT, its maximum drain current (IDmax) and VDD [11]. According to the manufacturer of the CGH4018OPP, CDS = 9.6 pF @ 28 V/1 MHz and CGD = 1.6 pF @ 28 V/1 MHz (per transistor cell). Its minimum saturated drain current is IDSmin = 23 A. These factors can be rearranged to calculate fmax from COUT and POUT in nominal Class-E conditions as follows:

Fig. 2 shows fmax for the CGH4018OPP at different POUT and VDD levels. Considering that POUT = 90 W is a safe output power level for the CGH4018OPP (per cell), from Fig. 2, fmax 818 MHz at VDD = 28 V. This frequency is clearly lower than the lower end of the target frequency band. Fig. 2 also suggests that fmax could be traded for POUT or VDD, but this solution involves increasing the peak drain current (IDpeak), and thus, decreasing the load impedance required by the transistor.

The model of the transistor provided by its manufacturer is a compiled one that also includes the effects of its package and it does not show the value of the components of the equivalent circuit of the transistor required for the design of the amplifier. Therefore, the model shown in Fig. 3 proposed by Sokol and Redl for transistors in switchmode operation [12] was used to find several parameters and equivalent circuit elements of the amplifier. The values obtained are shown in Table I; for simplicity, they are considered linear.

Fig. 3. Packaged transistor input and output ports models.


Input port components values
Output port components values
52 pF
11.6 pF
0.2 Ω
0.3 Ω
0.28 nH
0.1 Ω
0.08 pF
0.28 nH
8.65 Ω
0.08 pF
5.01° @ 1.2 GHz
8.65 Ω
5.01° @ 1.2 GHz

B. Class of Operation
The fmax provided by the CGH4018OPP is below the lower end of the L-band for the target POUT and VDD; nevertheless, the transistor still can operate safely in suboptimum Class-E at frequencies above fmax with very good performance. It can also achieve ηD similar to those achieved by other high-efficiency amplification classes such as Class-F or Class-F-1, but with the advantage of requiring a simpler load network that contributes to improve the power efficiency of the amplifier.

In [9] and [13]-[15], it is shown that the maximum achievable drain efficiency (ηDmax) for suboptimum Class-E is 97% at 1.56 fmax and 92% at 2 fmax. In addition, VDSpeak/VDD decreases down to 3.077 at 1.56 fmax, and 2.677 at 2fmax; note that VDspeak /VDD = 3.56 for nominal Class-E operation. These figures are similar to those obtained with other high-efficiency operation classes such as Class-F [16]-[18].

Similar to nominal Class-E, suboptimum Class-E operation above fmax requires a complex load at fundamental and pure ca-pacitive load at harmonics, being the phase angle of the load admittance at fundamental the main difference between the loads required by suboptimum Class-E and nominal Class-E. From [9], the optimum load value that maximizes the drain efficiency of an amplifier operating in suboptimum Class-E above fmax can be obtained. The angle of the optimum load required for suboptimum Class-E operation is shown in Table II for an ideal (lossless) transistor with zero switching times. The following two conclusions can be drawn from Table II.

  • There is an optimum load angle at fundamental for the sub-optimum Class-E amplifier that maximizes its drain efficiency. This optimum load angle depends on the f / fmax ratio.


Ang[YL n(f0)]
Ang[ZL n(f0)]
Fig. 4. Load network of the amplifier.
  • The load admittance versus frequency profiles required by nominal and suboptimum Class-E amplifiers are similar. Therefore, the load network used for nominal Class-E amplifiers can also be easily adapted for suboptimum Class-E operation.

C. Load Network
This amplifier was designed using the load impedance synthesis technique [19]; this means that the load required for suboptimum Class-E operation at fundamental and harmonics was synthesized and presented to the equivalent "switch" that models the transistor (SW in Fig. 3). This load depends on the reactance of COUT(XCOUT) at the highest operating frequency of the amplifier (XCOUT@1500 MHz), the power supply voltage (VDD = 28 V), and the output power level of the amplifier (POUT= 90 W). The load required by the amplifier can be approximately obtained from [9] and [20] considering all the factors mentioned before. For this amplifier, the load admittance at the fundamental frequency has been chosen to be YL(f0) = 0.1 S (-25°) at the center of the band (the load admittance angle at fundamental varies from -30° to -23° over the band of the amplifier) and the load admittance angle at harmonics to be 90°; these values were then adjusted using harmonic balance optimization over the entire amplifier bandwidth to achieve the desired output power and efficiency goals. This load admittance is presented to the switch SW over the complete bandwidth by means of a load network that trans-forms the 50-Ω impedance of the output port of the amplifier into the required admittance value.

The load network used in this amplifier is shown in Fig. 4. It is a double reactance compensation circuit that also provides impedance transformation functions and a port for dc voltage injection. Table III shows the values of the elements of the load network.

Load network component values

11.6 pF
11.6 pF
0.28 nH
6.95 pF
TLpckgOUT Z0
8.65 Ω
19.8 Ω
TLpckgOUT θ0
5.01° @ 1.2 GHz
TLO2 θe
10.55° @1.2 GHz
14.9 Ω
23.83 Ω
TLO1 θe
10.56° @1.2 GHz
TLO3 θe
91.62° @ 1.2 GHz

Three load planes marked as LP1, LP2, and LP3 are shown in the schematic of Fig. 4: LP1 is a virtual load plane located just at the equivalent switch SW that models the transistor. The load required for suboptimum Class-E operation of the amplifier must be provided at this load plane. LP2 is the actual drain-to-source load plane at the output of the transistor package, where load measurements can be carried out. LP3 is the 50-Ω load plane at the output of the amplifier.

Three sub-networks can be identified in this load network: LN1, LN2, and LN3.

  • LN1 is made up of COUT, the parasitics of the output port of the transistor package, LpckgOUT and TLpcksOUT, and two external components: a short microstrip transmission line, TLO1, and two paralleled ceramic multilayer capacitors, C2OA. These components are arranged as a π-type low-pass network, and thus are equivalent to a quarter-wave transmission-line transformer (in narrowband conditions).
  • LN2 is comprised by a short-circuited microstrip line that acts an inductor, TLO2, and another lumped ceramic multi-layer capacitor, C2OB. These components operate as a parallel resonant circuit. The short-circuited end of TLO2 is also used as a port to inject the power supply dc voltage VDD
  • LN3 is a microstrip quarter-wave transmission line transformer. LN3 carries out most of the load impedance transformation of the load network, and also contributes to achieve the double reactance compensation effect by keeping the load admittance angle approximately constant over the full amplifier bandwidth. The load admittance profile YL(f) achieved by this load network at the virtual plane LP1 is shown in Fig. 5. The double peak load admittance profile provided by this load network is responsible for the amplifier's double peak output power profile that will be shown later. As shown in Fig. 5, the phase and magnitude plots of the load admittance at the fundamental cannot be kept constant and parallel over the entire amplifier bandwidth; therefore, it is not possible to achieve both flat POUT and ηD simultaneously. In practice, it is more useful to achieve a flat POUT than a flat no; thereby, this amplifier was designed to provide flat POUT profile at the expense of a decrease of ηD at the upper end of the target frequency band.
Fig. 5. Load admittance profile provided at LP1 by the load network of the amplifier.

D. Input Network
With some exceptions [21], [22], the design of optimum driving methods and input networks for RF and microwave switchmode power amplifiers has not been covered in the technical literature, even though inefficient driving of switchmode RF power amplifiers directly translates into significant power gain (GP) losses (about 3 dB in most cases) that reduce their overall efficiency. Switchmode amplifiers using transconductance semiconductor devices, as the GaN HEMT used by the amplifier described in this paper, require a voltage waveform at the gate port capable of driving the device from "on" to "off" state, and vice-versa, with the shortest possible rise and fall times; in practice, times shorter than 30% of the switching period are considered sufficient for appropriate operation.

The trapezoidal voltage waveform is considered the most efficient waveform to drive switchmode power amplifiers [11], but device and package parasitics of most RF and microwave transistors make a trapezoidal voltage waveform very difficult to implement in practice. In the amplifier described in this work, CIN and inductive parasitic elements of the transistor precluded the implementation of trapezoidal voltage waveforms at its gate. Thus, a sine voltage is used to drive the amplifier at the expense of decreasing GP.

Another important feature demanded by switchmode power amplifiers is a flat GP profile to guarantee that a constant driving power level PIN can drive the amplifier over the entire bandwidth.

The input network of the amplifier proposed in this paper was designed to fulfill the two requirements mentioned above, while introducing minimum power losses and accounting for transistor and package parasitics. This input network is shown in Fig. 6; element values are shown in Table IV.

Three source planes SP1, SP2, and SP3, are shown in Fig. 6: source plane SP1 is a virtual plane located just at the left of the equivalent input capacitance of the transistor (CIN) and its equivalent input resistance (rIN). The source plane SP2 is located at the input of the transistor package (actual input impedance measurements can be obtained at this plane). Source plane SP3 is located at the 50-Ω input port of the amplifier.

Fig. 6. Input network of the amplifier.

Input network values

52 pF
16.69 pF
0.28 nH
3.9 Ω
TLpckgIN Z0
8.65 Ω
13.73 Ω
TLpckgIN θ0
5.01° @ 1.2 GHz
TLI2 θe
51.89° @ 1.2 GHz
19.58 Ω
24.57 Ω
TLI1 θe
15.72° @ 1.2 GHz
TLI3 θe
91.23° @ 1.2 GHz

The input network of the amplifier is made up of three subnetworks, as shown in Fig. 6: SN1 includes CIN and rIN, most significant package parasitics (LpckglN and TLpckgIN), and an external microstrip transmission line TLI1 SN2 comprises a short-circuited microstrip line TLI2, and a set of ceramic multilayer capacitors C2. The short-circuited end of TLI2 is used to inject the required negative gate to source bias voltage for the transistor Vbias. SN3 is a microstrip quarter-wave transmission-line transformer that carries out most of the source network impedance transformation.

This network provides flat (GV(f)) from the input port of the amplifier SP1 to the equivalent input capacitance of the transistor at SP3. It provides good performance regarding input re-turn losses (IRLs) at the upper end of the amplifier bandwidth; it must be noted that the required flat GV(f) profile from SP3 to SP1 is only possible at the expense of reflecting significant input driving power at the lower end of the bandwidth, and there-fore, at the expense of degrading IRL down to about -1 dB at 900 MHz. Fig. 7 shows GV(f) from SP3 to SP1 and |SP11| obtained with this network.

In order to achieve reasonable IRL performance, the two cells of the transistor were combined building a balanced amplifier by means of a hybrid quadrature combiner, as will be shown in Section III.

III. Amplifier Simulation, Building, and Testing

The amplifier was simulated and optimized using the harmonic balance simulator and optimizer of Microwave Office Design suite and the nonlinear model of the transistor provided by the manufacturer. In spite of the highly nonlinear nature of this simulation, it is important to point out that only minor convergence problems were found during the process. Fig. 8 shows simulated POUT(f) of the amplifier (for one cell of the CGH40180PP) for VDD values ranging from 12 to 28 V. Fig. 9 shows the simulated obtained at similar conditions.

Fig. 7. GV profile from SP3 to SP1 and |S11| at SP3 versus frequency.
Fig. 8. Simulated POUT (one transistor cell).
Fig. 9. Simulated ηD (one transistor cell).

From Fig. 8, it can be observed that POUT(f) is flat from 900 to 1500 MHz, with a smooth double peak shape that comes from the double peak load admittance profile shown in Fig. 5, as mentioned before. Fig. 9 shows ηD(f); it decreases with frequency, but it is still high (close to 80%) at the upper end of the target bandwidth. The dependence of ηD on VDD is moderate.

Fig. 10. Full schematic of the power amplifier.
Fig. 11. Photograph of the amplifier.

In order to test the accuracy of the simulation results, a basic manually controlled harmonic load-pull study was carried out on the transistor using a harmonic controlled load-pull test-bench [23]. The load—pull tests confirmed and validated the reasonable accuracy of the design hypothesis and the simulation results.

A prototype of the amplifier was built on 0.508-mm-thick R04350B substrate from the Rogers Corporation. The layout of the amplifier was carefully designed in order to minimize any additional parasitic elements. It was found, as expected, that the correct placement of lumped components was crucial to achieve the predicted performance. The full schematic of the amplifier is shown in Fig. 10. Fig. 11 shows a photograph of the amplifier.

Both POUT and ηD were measured in CW conditions using a calibrated test bench comprising a 40-dB attenuator and an N1912A Agilent power meter. The results are shown in Figs. 13 and 14 for VDD ranging from 12 to 28 V.

The results shown in Figs. 12 and 13 were obtained by injecting constant input driving power PIN = 36 dBm over the entire amplifier bandwidth. Simulation results shown in Figs. 8 and 9 and the measured results shown in Figs. 12 and 13 were in good agreement.

POUT and ηD were also measured in pulsed mode (pulse width = 1 ms, pulse repetition frequency PRF = 100 Hz). The amplifier can provide up to 94 W in pulsed mode (per cell) versus up to 90 W in CW conditions. Measured peak drain efficiency was 90% @ 28 V in pulsed operation versus 85% ( 28 V in CW conditions.

Fig. 12. Measured POUT in CW (one transistor cell).
Fig. 13. Measured ηD in CW (one transistor cell).

Fig. 14 shows the measured PAE for different values of VDD. The strong dependence of the PAE on VDD is caused by the Gp dependence on VDD, which is a common feature of switchmode amplifiers; it ranges from GP = 15 dB @ 28 V to GP = 8 dB @ 12 V. Maximum PAE is achieved for VDD = 28 V.

Fig. 15 shows POUT versus PIN in CW operation for VDD = 28 V at 1000, 1200, and 1400 MHz. Note that the amplifier can also be used below compression providing GP about 20 dB at the expense of lower ηD.

The two cells of the CGH4018OPP were used to build two identical amplifiers that were combined into a balanced amplifier using two 3-dB 90° hybrid combiners (1E1305 from Anaren) to double the output power and to decrease input standing wave ratio (SWR) down to acceptable levels. Since POUT of the balanced amplifier exceeds the maximum power rating of the combiner in CW, the amplifier can only be operated at its maximum output power in pulsed mode at 50% duty cycle. Note that the amplifier is able to operate in CW mode at full power if a suitable hybrid combiner with a higher power rating was used. This happens only for VDD higher than 20 V, corresponding to POUT > 100 W.

The measured output power of the hybrid amplifier (POUTCOMB) and its drain efficiency (ηDCOMB) operating in pulsed mode (pulse width = 1 ins, PRF = 100 Hz) are shown in Figs. 16 and 17, respectively, for VDD ranging from 12 to 28 V.

Fig. 14. Measured PAE in CW (one transistor cell) for different power supply voltages.
Fig. 15. POUT versus PIN performance the amplifier.
Fig. 16. Measured POUTCOMB in pulsed mode.

As mentioned before, one of the benefits of using a balanced amplifier topology is an important improvement of the ERL and input SWR. Fig. 18 shows the measured input SWR and |S11| of the balanced amplifier.

One of the most important and promising applications for this circuit is to operate as an RF stage in an envelope elimination and restoration (EER) or envelope tracking (ET) amplifier; both VDD - AM and VDD PM performance need to be well characterized in this application [24]. Fig. 19 shows the measured VDD - AM and VDD - PM at 1300 MHz. From these figures, VDD - AM conversion appears negligible, but VDD - PM conversion (caused by the nonlinear nature of COUT) would need to be corrected by predistortion to achieve reasonable linear performance in EER/ET applications [25], [26].

Fig. 17. Measured ηDCOMB in pulsed mode.
Fig. 18. Measured input SWR and |S11| of the balanced amplifier.
Fig. 19. Measured VDD - AM and VDD - PM conversion plots.

Fig. 20 shows a demodulated 1300-MHz pulsed RADAR signal (pulse width = 1 ins, PRF = 100 Hz, POUTPEAK = 180 W) that can be used to analyze the pulse operation performance of the amplifier [27]. The demodulated pulse does not show fading, and consequently, no gain compensation circuit is required.

Fig. 20. Demodulated pulse amplified by this amplifier, pulse width = 1 ms, PRF = 100 Hz, POUTPEAK = 180 W.
Fig. 21. Measured harmonic levels versus frequency.

Fig. 21 shows the measured harmonic level of the amplifier, most significant harmonics are below 30 dBc.


Frequency (GHz)
Gain (dB)
ηD / PAE (%)
2006 [28]
50 / -
2009 [29]
0.6 - 1
87.8 / 80.6
2011 [30]
1 - 2
- / 50
2011 [31]
- / 74
2011 [32]
81 / 73
2011 [33]
1.2 - 2
84 / 79
2012 [34]
1.2 - 1.3
60 / -
This work
0.9 - 1.5
85 / 81
S.O. Class-E

IV. Conclusion

A high-efficiency wideband high-power L-band suboptimum Class-E power amplifier based on a packaged (but unmatched) GaN HEMT has been demonstrated in this paper. It covers the main RADAR sub-bands at L-band without the need for manual adjustment, exhibiting 50% fractional bandwidth at a center operating frequency of 1200 MHz. It provides output power up to 180 W and drain efficiency in excess of 80% over almost its entire bandwidth. To the best of the authors' knowledge, the performance of this amplifier outperforms other amplifiers for the same frequency band and output power 'level, especially commercial grade ones, as shown in Table V. A simple low-loss double-reactance compensation and impedance transformation network that includes the transistor die and package parasitics provides the load admittance required by its equivalent switch to operate in suboptimum Class-E. The input network of the amplifier has been designed to provide constant GP over the complete operation bandwidth. This amplifier can be directly used in most RADAR applications in the L-band and also as an RF base stage in EER and ET transmitters for services such as digital audio broadcasting (DAB) or mobile satellite communications. Its repeatability enables simple combination of amplifier units to achieve higher output power levels. The design principles presented in this paper can be easily applied to larger GaN devices as soon as they become available in the market, and they can also be extended for designs at higher frequency bands.

The amplifier is based on suboptimum Class-E operation, a high-efficiency amplification mode not very widely used and known. However, it has been shown that this class of operation allows a transistor to provide very high efficiency at frequencies above its maximum frequency for nominal Class-E operation, offering performances similar to other high-efficiency modes commonly used at this frequency bands (such as Class-F or Class-F-1) and requiring a simpler load network.


The authors are grateful to Wolfspeed, Inc. for supporting the publication of this paper. The authors want to thank M. Rodriguez-Gonzalez for his great work checking this paper's manuscript.


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[34] S. Rochette, 0. Vendier, D. Langrez, J. Cazaux, M. Kuball, M. Buchta, and A. Xiong, "A high efficiency 140 W power amplifier based on a single GaN HEMT device for space applications in L-band," in 7th Eur. Microw. Integr. Circuits Conf, Amsterdam, The Netherlands, Oct. 2012, pp. 127-130.

Francisco Javier Ortega-Gonzalez, photograph and biography not available at time of publication.

David Tena-Ramos, photograph and biography not available at time of publication.

Moises Patiiio-Gomez, photograph and biography not available at time of publication.

Jose Manuel Pardo-Martin, photograph and biography not available at time of publication.

Diego Maduelio-Pulido, photograph and biography not available at time of publication.

Manuscript received May 18, 2013; revised August 05, 2013; accepted August 06, 2013. Date of publication September 05, 2013; date of current version October 02, 2013.

F. J. Ortega-Gonzalez, D. Tena-Ramos, M. Patiño-Gomez, and J. M. Pardo-Martin are with EUIT de Telecomunicacion, Centro de Electronica Indutrial, Grupo de Ingenieria de Radio, Universidad Politecnica de Madrid, 28031 Madrid, Spain (e-mail:

D. Madueño-Pulido is with Indra Sistemas, 28850 Torrejón de Ardoz, Spain. Color versions of one or more of the figures in this paper are available online at

Digital Object Identifier 10.1109/TMTT.2013.2279366

Copyright © 2013.

This material is posted here with permission of the author. Such permission does not in any way imply author’s endorsement of any of Wolfspeed’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the author by writing to By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

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