Communications Infrastructure

Resolving mMIMO PA Design Challenges

Abdulrhman Ahmed, Jangheon Kim, Christian Eppers; Wolfspeed. Noureddine Outaleb; ADI Wireless System Group.
Oct 20, 2021
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Resolving mMIMO PA Design Challenges


Massive multiple-input-multiple-output (mMIMO) system designers are being challenged to improve overall system efficiency.  With instantaneous bandwidths at 200 MHz and greater, it is increasingly important to reduce the distortion created when operating Power Amplifiers (PA) in their non-linear region.  Balancing wideband system linearity with the system efficiency is a must-meet metric to fit the size, weight, and power requirements of mMIMO systems.  To design such a wideband system around given linearity requirements, the optimization of the design should look beyond the final-stage PA and expand focus to the entire amplification lineup. Similarly, this amplification lineup should be optimized with the system transceiver and Digital Pre-Distortion (DPD) algorithm in mind.

In a collaboration between Wolfspeed and Analog Devices, Inc. (ADI), we take a deeper look at the balance between efficiency and linearity by discussing industry approaches and presenting examples in the following areas:

  1. Choosing higher efficiency device technologies, i.e. Gallium Nitride (GaN) on Silicon Carbide (SiC), for amplifier lineups.
  2. Application specific DPD systems for simple and highly efficient lineup architectures.


The rapid growth of Fifth Generation (5G) mobile communications and the expansion of the internet of things (IoT) is bringing higher data rates to an ever-increasing number of users, enabled by high efficiency semiconductor technologies such as Gallium Nitride (GaN) on Silicon Carbide (SiC).  High data rates allow for fast data transfer, more users, and improved service quality.  To deliver these services, higher-order modulation schemes and very wideband signals are being used. These characteristics bring increased data rates in wireless transmission to new levels.  This makes the transmit (TX) chain requirements tougher, since the transmitter’s nonlinearities are excited more aggressively.

The Power Amplifiers architecture used in both 4G and 5G systems is the Doherty amplifier.  This architecture maintains peak efficiency over a power back-off window.  This can come at the expense of being saturated even at power back-off.

In 4G applications, PAs were designed for relatively narrowband applications (approximately BW = 60 MHz).  In these applications, the linearizability problems are caused mainly by the final stage Doherty PA.

For 5G mMIMO applications, the required instantaneous bandwidth is 160 MHz or greater. With such wideband signals, the linearizability problems can be a combination of the entire PA lineup, wideband transceiver, and the digital predistortion system. Thus, the linearization over the wider band is influenced by the entire system.

In addition to the wideband requirements, high efficiency is another key metric for 5G systems.  Efficiency requirements are must-meet conditions to fit the size and weight requirements of mMIMO active antenna systems. High efficiency power amplifiers typically use an asymmetrical Doherty architecture. The drawback to this approach is the potential for highly nonlinear performance.

These opposing design elements of linearity and efficiency become trade-off parameters in PAs.  To maximize the efficiency, PAs are designed with a minimum linearity requirement and the DPD system ensures system level linearity requirements are met.

When designing wideband PAs to meet a specified linearity requirement, the optimization of the design should focus on the entire amplification lineup as previously indicated.  Similarly, the lineup should be optimized with the transceiver system and DPD system in mind.

Power Amplifier Module for mMIMO

Wolfspeed, a leader in GaN on SiC device technologies; is a vertically integrated semiconductor material and device business offering world class GaN RF power amplifiers and transistor devices. This enables a reliable supply of GaN front-end modules from the bulk crystal, epitaxy, wafer, die, device design to world-class PAs.

Design Topology

Wolfspeed’s high-power multi-chip asymmetrical Doherty PA module (PAM) is designed using state-of the-art GaN on SiC HEMT devices and accurate non-liner device models [1] for 5G mMIMO base station applications. The PAMs are designed in a compact surface mount package, which is a much smaller than discrete component solutions.

The modules require minimum external components to build a fully functional, high-performance Doherty PAM. The asymmetrical Doherty PAM is suitable for both 4G and 5G design standards, featuring a 48 V supply voltage within a 6 × 6 mm surface mounted package. For improved efficiency, the second harmonic termination is integrated within the package.        

Figure 1.0:  Wolfspeed Lineup PAM EVB

Current production PAMs cover the sub-6 GHz mobile frequency band in the range of 2.3 GHz to 4.0 GHz. 

  • WS1A3940:  Module optimized for the US C-band 3.7 to 4.0 GHz designs
  • WS1A3640:  Module optimized to operate frequency from 3.3 GHz to 3.8GHz.  It has the design flexibility for operating in single bands such as B42 and B43 design
  • WS1A2639:  Module optimized for frequency band designs in the B41 range (2.496 GHz to 2.69 GHz range)

For creating a full amplifier lineup, the WSGPA01 general purpose amplifier was created as a driver stage to support the performance of the above devices operating in bands up to 5 GHz.

All the PAM devices demonstrate (Table 1.0) excellent linearizability at the average output powers of 38.5 dBm to 40 dBm, deliver greater than 13.0 dB power gain, and high saturated power greater than 47 dBm.  Performance was demonstrated using an Analog Devices, Inc. DPD system with instantaneous bandwidth (IBW) up to 200 MHz and 8 dB peak to average power ratio (PAPR) signal,

PAM Part Number
Frequency band (MHz)
iBW (MHz)
Pout (dBm)
Gain (dB)
Efficiency (%)
Peak Power (dBm)
WS1A3940 (US C-band)
3700 -3980
WS1A3640 (B42)
3400 - 3600
WS1A3640 (N78)
3300 - 3800
WS1A2639 (N41)
2496 - 2690
Table 1.0: RF performance of the PAMs under the LTE signal

Digital Pre-Distortion (DPD)

Over the last decade, ADI integrated transceivers have matured into a high-performance platform. The ADI RadioVerse™ family includes a wide range of integrated transceivers that support up to 200 MHz of occupied bandwidth, integrating advanced features like DPD, Crest Factor Reduction (CFR).

DPD Measurements

Developing a PA with a bandwidth capability of 200 MHz and higher that meets 3GPP specifications and is optimally efficient is a significant challenge. To avoid the non-linearity effects in the TX chain, the solution is to use a capable DPD algorithm [2, 3, 4]. DPD is a PA linearization technique that estimates the PA behavior model and then cancels out non-linear and memory contributions. This allows the PA to operate at higher power and at higher efficiency. The basic DPD operating principle is depicted in Figure 2.0. There are many DPD models proposed in the literature. Most of them being simplifications of the Volterra series such us the generalized memory polynomial (GMP) [4, 5] and the memory polynomial (MP) [6].

Figure 2.0: DPD operation basic principle

PAs and DPD share a partially symbiotic relationship. That relationship can both harmonious and difficult.  DPD systems optimized for a particular PA design may not be able to sufficiently correct for another PA design.

Often, optimal performance is achieved when both DPD and PA are configured and tuned in unison to match the specific application. For this reason, ADI and Wolfspeed have collaborated to ensure the system [ADI TRx ↔ DPD ↔ PA] is optimized together. Close collaboration is crucial as bandwidth requirements increase.

Challenges are evenly balanced across the collaboration.  The Wolfspeed PA developers are challenged to achieve wider bandwidths while maintaining the high overall RF performance.  ADI DPD developers are challenged to develop optimized DPD algorithms which meet the 3GPP specs with minimum DPD resources and minimum system power consumptions.

The AD9375 is the first ADI RF transceiver with an on chip DPD algorithm. The AD9375 DPD solution supports 3G and 4G waveforms with an instantaneous signal bandwidth of up to 50 MHz.

For 5G systems (also for 3G and 4G) with bandwidths up to 200 MHz, the ADRV9029 has two DPD solutions (Gen3 and Gen4) and was released last year.

ADI’s next generation transceiver features a more powerful DPD algorithm (Gen5) with a faster adaption rate and a higher sampling DPD rate enabling the 400 MHz 5G system requirements.  It also features an embedded GaN Charge Trapping Correction (CTC) IP which improves the GaN EVM compliance in TDD systems and enhances further the dynamic traffic performance. The new 8T8R transceiver features a faster recovery time which allows real-time recovery and stability [7].

Next Gen TRX
ADI DPD Evolution
Tech Node
650mW max.
Table 2.0: ADI DPD Model/Transceiver Evolution

Using an embedded DPD in the transceiver SoC reduces power consumption by 90% over FPGA based solutions and cuts the number of SERDES lanes in half.  Thereby reducing FPGA requirements and cost. Table 2.0 demonstrates the ADI DPD model evolution with corresponding IBW capability.  The table also shows as the system bandwidth capability increases, continuous effort is made to further reduce the DPD power consumption.

These transceiver characteristics simplify design, reduces system size, weight, power, and costs of Small cell, mMIMO, and Macro-cell base stations.

To validate and optimize the different DPD algorithm generations, Wolfspeed made available its mMIMO PA Modules portfolio to ADI for this exercise. The collaboration focused on the evaluation of jointly optimize multiple mMIMO system solutions. The Wolfspeed mMIMO PAM portfolio mentioned earlier was evaluated with all ADI DPD algorithm variations.

Figure 3.0 and Figure 4.0 highlight the ADI transceiver – Wolfspeed PA system performance across ADI’s DPD algorithm evolution, with signal bandwidth of 160 MHz and 200 MHz, respectively. In these figures, the 3GPP emission specification requirements are met with margin with signal bandwidth to up 200 MHz. Significant margin is achieved with the ADI Gen5 DPD as this linearization algorithm is more powerful and it is aimed for 400 MHz IBW mMIMO systems.

Figure 3.0: ADI DPD evolution with Wolfspeed mMIMO PAMs – 160 MHz IBW
Figure 4.0: ADI DPD evolution with Wolfspeed mMIMO PAMs – 200 MHz IBW

ADI and Wolfspeed are currently working on validating the next 5G system bandwidth requirement of 400 MHz. This high-bandwidth requirement adds more challenges on the PA design side and on the DPD algorithm development side.  The main challenge still the high-system efficiency requirements by customers on both the radio and the PA components. This constrains the PA to be efficient over the entire broadband operation which is challenging with a Doherty PA architecture.  The challenge is the same on the DPD algorithm side in which the resources are constrained for minimum power consumption while still meeting the 3GPP specs.

Figure 5.0: ADI DPD evolution with Wolfspeed mMIMO PAM

Figure 5.0 reports the linearized system ADI TRX DPD (Gen5) - WS1A3640 n78 PA lineup ACLRs versus the signal BW. With this system lineup the specs are met with margin for bandwidth up to 340 MHz. ADI and Wolfspeed are both focusing on optimizing the system components to meet the 400 MHz bandwidth requirement at maximum efficiency.


5G system optimal performance is achieved when both the DPD and the PA are tuned together. The collaborative efforts by Wolfspeed and Analog Devices, Inc. demonstrate solutions to achieve a linear, efficient, and wideband communication system by closely coupling the development of Power Amplifier design with Digital Pre-Distortion systems for wide-bandwidth mMIMO devices.

To learn more, go to and for product information.

Article originally published on Microwaves & RF.


  1. Cree-Wolfspeed, “GaN HEMT Large Signal Models” . May 08, 2020.
  2. J. K. Cavers, “Amplifier linearization using a digital predistorter with fast adaptation and low memory requirements,” IEEE Trans. Veh. Technol., vol. 39, pp. 374–382, Nov. 1990.
  3. A. N. D’Andrea, V. Lottici, and R. Reggiannini, “Nonlinear predistortion of OFDM signals over frequency-selective fading channels,” IEEE Trans. Commun., vol. 49, pp. 837–843, May 2001.
  5. D. R. Morgan and al., “A Generalized Memory Polynomial Model for Digital Predistortion of RF Power Amplifiers”, IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 54, NO. 10, OCTOBER 2006, pp. 3852-3860.
  6. L. Ding, G. T. Zhou, D. R. Morgan, Z. Ma, J. S. Kenney, J. Kim, and C. R. Giardina, “A robust digital baseband predistorter constructed using memory polynomials,” IEEE Trans. Commun., vol. 52, no. 1, pp.159–165, Jan. 2004.
  7.  S. Summerfield and F. Kearney, “How to Make a Digital Predistortion Solution Practical and Relevant”, Analog Devices, Vol 55, No 3 – August 2021.
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