Evaluation Board For Paralleling 1200V C3M Silicon Carbide MOSFETs in a 7-pin TO-263 Package

The purpose of this evaluation board is to demonstrate the proper design and layout for paralleling two high performance Wolfspeed^® Silicon Carbide (SiC) MOSFETs in a 7-pin D2PAK™ package. This evaluation board comes configured as a half bridge but it can be configured into other common topologies such as a synchronous boost or synchronous buck topology. This board was designed to make it easy for the user to:

• Evaluate dynamic and steady-state current sharing of parallel SiC MOSFETs
• Evaluate SiC MOSFET switching performance and characterize E_ON and E_OFF losses in SiC MOSFETs.
• Evaluate SiC MOSFET thermal performance in a synchronous buck or boost converter.
• Use as a PCB layout example for effectively paralleling SiC MOSFETs.
• Use as a reference for thermal management of a D2PAK SiC MOSFET

Wolfspeed and Keysight Technologies, Inc. have worked together to develop a PathWave Advanced Design System (ADS) workspace for this evaluation board that allows designers to simulate the design including parasitic effects of the PCB layout. This workspace demonstrates how to use the ADS platform to optimize a PCB layout for paralleling Silicon Carbide MOSFETs faster and at lower cost than a conventional prototype-test design cycle. For details on the ADS workspace and to request a trial license, click here.

Specifications

• Max DC Bus Voltage of 900 V
• Rated Power of 10 kW @ 60 kHz (synchronous boost operation 400 V-800 V)
• Optimized locations for scope probe measurements of drain current, V_GS, and V_ds
• Synchronous and asynchronous buck and boost topologies supported
• Can be configured as full bridge DC/DC by using two evaluation boards