Engineering for Outcomes: Three Ways Wolfspeed Gen 5 Achieves Real-World Performance

I’ve been fortunate in my role leading power R&D to be in the room for many challenging conversations about what Wolfspeed’s device roadmaps should entail. I’ve also been fortunate to be with Wolfspeed long enough to hear and acknowledge the feedback from customers that we simply weren’t innovating fast enough.

Although that humbling feedback is in the rear-view mirror, it did set off a chain of decisions that’s brought us to where we are today: Introducing our second technology generation in less than two years. I give my team kudos for the massive improvement in innovation cycle time; however, it’s not just our speed that’s different. We’re much more intentional about “customer centricity.” What’s been central to Gen 4 and Gen 5 is their ability to perform not just at perfect operating conditions, but in the real-world – when temperatures, installation locations, and operating profiles aren’t as predictable. That’s been our key motivator. But how we get to this real-world performance is just as deliberate as our design philosophy.

Let’s walk through it.

I’ve been asked quite a bit what the “best” power device technology type is, and it’s a fair question. With cell design architectures like trench, super junction or even JFETs nabbing headlines, it’s easy to see why. Trench and super junction offer compelling means to achieving improvements in figures of merit like R_DS(ON). Honestly speaking, our team is keeping all options on the table for future development.

We ultimately chose to continue turning knobs on our existing planar MOSFETs for two reasons. First, because we could! Our planar design had the innovation “headroom” that justified optimizing on what we had already figured out. Secondly, and more importantly, our customers are familiar with power planar-based MOSFETs. We’ve already gone through the growing pains with them of qualifying and manufacturing at scale on 200 mm planar-based wafers, so why put them through having to re-design and re-validate something new if they don’t have to?

Sure, cell design architecture is certainly a path to improved performance, but for us at Wolfspeed, it was just one decision to make. Let’s unpack three additional ways we achieved the “real-world” performance of Gen 5:

1. Our material scientists made excellent epitaxy possible.

My team knew that to optimize Gen 5 not just for “typical” performance, but for worst-case scenarios, we needed tightened epi distributions — specifically better epi doping and thickness uniformity across the die. Not only did our materials team hit the mark with excellent epitaxy, they ultimately helped us achieve a +/- 18% R_DS(ON) distribution, which eliminates the need for our customers to build in unnecessary design margin within their systems.

2. We got creative with unit cell structure and hyper-fixated on active area

Although we decided against using trench or super junction designs for Gen 5, we still pushed ourselves to increase MOSFET channel density. With a few non-trivial modifications to our hex cell design we were able to further reduce the resistance, enabling higher current for the customer. We also took a ruthless approach to die layout, scrutinizing every single inactive portion of the device. We achieved a 12% active area improvement for 1200V, and a 6% improvement for 750V which plays a big role in improving R_DS(ON) and blocking voltages.

3. We built upon the soft body diode technology introduced in our Gen 4 MOSFETS

The Gen 4 soft body diode reduces voltage overshoot throughout the switching cycle, which helps designers overcome the following challenges:

• It reduces switching losses for all applications, even more demanding ones like automotive and data center server applications that require low losses and high reliability.
• It mitigates system-level risks with reduced peak voltages.
• It enables faster switching speed, serving as a fundamental building block for discrete applications.

Altogether, these approaches plus a few additional design tweaks drove a compounding effect for what this new generation could achieve: Super low RSP at high temp, so our customers can continue pushing their next generation programs further.

In Wolfspeed’s case, Gen 5 highlighted what our R&D and engineering teams are capable of when we focus first on actively listening to what the customer expects, then focus on how we get there. I’m sure I’ll still get asked how much life Wolfspeed planar has ahead of itself — we engineers truly can’t help ourselves. What I’ll say is this: We’ll only commit to a new generation once we’ve heard loud and clear what the customer requires, and then we’ll engineer that MOSFET design (whatever it may be) to absolute entitlement.

For now, we want your feedback on how current or future Gen 5 new product introductions (NPI) can help resolve the application-specific hurdles you’re facing. If you’d like more information, please reach out to us. We’re looking forward to partnering.