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Silicon Carbide

Designing with Silicon Carbide for High Efficiency Renewable Energy Systems

Apr 14, 2023
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Solar power inverters and ESS applications along with other renewable systems are modernizing energy grids to improve resilience, meet global energy requirements and reduce their overall carbon footprint. These systems must be as efficient as possible in rugged environments as well as compact and inexpensive.

Silicon Carbide solutions tick all the boxes for renewable energy systems that depend on semiconductors because they enable increased power density, lower switching losses and higher switching frequency. Wolfspeed Silicon Carbide solutions enable lighter, smaller, and more efficient solar inverters for solar power semiconductors that absorb sunlight and convert it to electricity in environments that experience fluctuating ambient temperatures, high humidity, and other harsh conditions.

For ESS applications, Wolfspeed Silicon Carbide is the gold-standard technology because our Silicon Carbide MOSFETs and diodes offer higher performance and lower losses while allowing engineers to create systems that use fewer components, thereby keeping overall system size and cost down.

SiC technology runs cooler and faster and enables smaller and lighter power electronics with higher energy efficiencies because of innovation and best practices at the PCB design stage. Let’s review some of the challenges and tips for PCB layout design at the device, sub-circuit, and system levels.

PCB Layout Determines SiC Success

SiC-based systems leverage superior switching characteristics coupled with low conduction losses to enable higher switching frequency than is possible with silicon.

These desirable traits create challenges because the high voltage slew rates (dv/dt) and current slew rates (di/dt) inherent to SiC power devices make these circuits sensitive to crosstalk, false turn-on, parasitic resonances, and electromagnetic interference (EMI).

Device Level

Proper creepage and clearance distance between components at the device level is critical because the spaces between MOSFET legs/ PCB traces help to eliminate flashover or tracking between them. A variety of safety standards prescribe different spacing requirements depending on the voltage, application, and other factors.  

IPC standards can also be used as a guideline whose aim is to standardize the assembly and production requirements of electronic equipment/assemblies. Although not mandatory, the IPC- 2221 Generic Standard on Printed Board Design and IPC 9592 Performance Parameters for Power Conversion Devices standards can be used as guidelines to estimate minimum spacing between conductors on a PCB.

Proper creepage between the SiC MOSFET and heatsink is essential. In solar applications, heatsinks are large and mechanically fixed to chassis, so horizontal mounting tends to be quite common, and often the extension of the isolation pad slightly over the bent of the terminals can increase creepage in this case. Owing to different shapes of chassis, sometimes the terminals must be bent at an angle.

Sub-Circuit Level

Higher slew rates combined with parasitic capacitances and loop inductance make circuits more sensitive to crosstalk, false turn-on, voltage overshoots, ringing and potential EMI issues.

At this level, a SiC gate drive is used to turn a power semiconductor on and off; depending on different elements, oscillations and overshoots might occur at gate. Oscillations can be controlled with higher damping, which is directly proportional to gate resistance and inversely proportional to gate loop inductance – a low inductive gate loop enables higher damping without compromising on the slew rates.

A PCB layout for a SiC gate drive should include a compact gate loop to dampen gate resistance and reduce oscillatory voltage, making the gate drive less susceptible to external magnetic fields. Parasitic capacitances must also be minimized during the PCB layout because along with high dv/dt they can result in crosstalk, false turn-on, and increased switching losses – they also determine slew rates and can help to minimize the impacts of high electric and magnetic fields.

Your PCB layout at the system level affects cooling. So does careful component placement, which plays a key role in optimizing the switching cell.

System Level

Minimizing EMI and protecting shield sensitive signals from high magnetic and electric fields is especially critical, so PCB layout should favor placing input and output connectors on opposite sides of the board to avoid noise coupling, while the Input EMI filter and input/output connector should be placed far away from high dv/dt trace/nodes to avoid noise coupling. Sensitive signals, including gate loop and control signals, should be placed far away from high dV/dt trace/nodes and from the high magnetic field such as PFC choke, DC-DC power magnetics.

Component placement can improve or deteriorate cooling, which depends on the size of the copper plane and number of layers used for heat dissipation, thermal via diameter, spacing, and copper thickness. Make sure MOSFETs aren’t placed close to other heat sources, including other power semiconductors, while using a copper plane, preferably on multiple layers, will dissipate heat away from the MOSFET.

Wolfspeed Silicon Carbide enables smaller, lighter, and more cost-effective design, converting energy more efficiently to enable countless new clean energy applications including solar power and ESS. Read more about PCB design challenges in power electronics systems and how Wolfspeed Silicon Carbide discrete devices enable higher efficiencies on

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