Cut Down on Hours of Comparative Analysis with the SpeedFit Design Simulator
Many applications are benefiting from Silicon Carbide (SiC) components due to the major advantages seen over traditional technologies such as those based on silicon and insulated-gate bipolar transistors. But characterizing a design with SiC components is not always a straightforward process. Whether developing a new product or upgrading previous designs, it’s best to simulate and optimize components during the earlier design phases before topologies and device selection are set in stone.
The SpeedFit Design Simulator is an online PLECS-based, system-level circuit simulator intended for aiding in several key areas, such as device-to-device and topology comparisons, parallel design configurations, thermal management, and evaluating hardware performance such as semiconductor losses and inductor/transformer waveforms to help home in on a particular topology or chipset.
SpeedFit switching and conduction loss modeling
For a SiC MOSFET, there are three typical sources of loss that can be analyzed. The first is the loss during switching while turning on (Eon), the second is loss during switching while turning off (Eoff), and the final loss is from conduction during “on” time (represented as Pconduction). Thus, the total power loss can be described as:
Figure 1 shows the gate signal pulse and how Vds, Ids, and Ploss are related to the on/off portions of the signal.
While on, the conduction power loss is dependent on junction temperature (TJ) and drain current (ID). Several VDS versus ID curves at different temperatures are stored in a lookup table, and the “on” voltage is found via interpolation. The off-state power loss is negligible, as the leakage current is very low.
The switching losses are dependent on VDS, IDS¬, TJ, and the external gate resistance (RG). 3-D lookup tables of switching loss as a function of ID, off-state voltage and temperature are used to determine the Eon and Eoff values at each switching event. These results are then scaled by the external gate resistance (RG) selected. When measuring total average device losses, the general goal is to calculate the total conduction and switching energy lost during a switching cycle, then output as an average power pulse during the following cycle. This can be achieved by measuring with a probe and observing periodic average (conduction loss) and periodic impulse average (switching loss) blocks, which average out the result (see Figure 2).
SpeedFit is able to simulate both electrical and thermal properties, then uses lookup tables to determine losses for the current switching cycle, and adds that to a thermal circuit (including a heatsink). For the electrical circuit, the simulation will calculate current and voltage applied to the switches and then supply that data to loss lookup tables after each switching event. In the thermal domain, TJ is estimated and updated based on previous cycles and current cycle losses. The resulting TJ is fed back to lookup tables for the next cycle. Figure 3 demonstrates this simulation.
How to run configurations and simulations
When starting an application with SpeedFit, the user will need to select Application, Input the operating parameters and topology, select the Device(s), set Thermal Parameters, run the Simulation, and then print the Summary report. A user guide is available that includes helpful tips and range limitations for each topology.
When selecting the Application, there will be a few converter types to choose from (DC/DC, AC/DC, and DC/AC). For multi-stage converters such as an active front end followed by a CLLC DC/DC stage, a separate simulation should be performed for each stage.
When Inputting the operating parameters (see Figure 4), start by selecting the desired topology (if known), or directly enter the inputs/outputs to see matching circuits. The parameters shown to the user will change based on the topology selected, and “resonant based” topologies have buttons that can automatically populate suggested resonant component values for simplification.
After voltage and current ratings are determined, the Device tab will display a short list of recommended devices, along with an optional longer/complete list of all devices available (MOSFETs, diodes, modules). During this process, the user can adjust the number of parallel devices to be used, along with the gate resistance. Additionally, when using discrete MOSFETs in AC/DC or DC/AC applications, a Schottky diode may be added in parallel to the MOSFET to reduce losses during switching.
When setting Thermal parameters, the internal thermal junction resistance (Rth,JC) is included automatically; however, the user is required to enter the thermal interface resistance (Rth,ch). This interface resistance is counted on a per-switch basis. Power modules with multiple switch positions will include two, four, six, or more parallel Rth,ch based on the number of switches in the module. Heatsinks can either be variable or fixed, depending on the application. A variable heatsink consists is modeled as a thermal impedance to ambient (Tamb) and includes a time constant. For the fixed heatsink option, a heatsink temperature must be specified. For topologies with primary and secondary side SiC devices, a separate (but identical) heatsink is used for each side.
The Simulate tab shows the topology, heatsink configuration, and key parameters specified by the user (see Figure 5). Before simulation, passive component parameters in the circuit can be adjusted to tailor the design to match the application and better optimize results. After simulation, waveforms are shown and indicate source voltage, load voltage, input current, load current, and diode/MOSFET voltage and current. A system overview table provides readout of power, switching frequency, and efficiency, while the device overview table provides readouts on losses and estimated junction temperature. The losses displayed in the device overview table are the combined losses of all devices of the type shown. For example, in Figure 5, the combined losses of all 4 primary SiC MOSFETs is 54.54W.
The user can run additional iterations of the same topology to compare results and optimize the design. First, the user clicks the “hold result” button on the simulation tab to keep previous results for reference, then inputs another operating point or evaluates an alternative device, and re-simulates the new conditions.
Lastly, the Summary tab provides a detailed overview of the results for multiple simulated runs (called “Variants”) and a side-by-side comparison. The User Guide tab, meanwhile, provides a table of operating limits for each topology while explaining the parameters of each tab. It also provides example data to use for various thermal situations, which provides a good first approximation when designing a new system in which the thermal impedance has not yet been characterized.
SpeedFit application examples
Let’s run through an example application: a 45-kW three-phase inverter that is air-cooled, is powered by an 800-V bus, outputs 480 V, and is switched at 10 kHz. The goal here is to evaluate Wolfspeed’s WolfPACK dual SiC MOSFET module and discrete SiC MOSFETs.
For this example, four options (two discrete and two modules) were easily assessed in just minutes with several possible solutions, all of which included efficiencies of >99%. The solutions consisted of:
These results can be used as inputs for a complete system architecture assessment looking at various tradeoffs, such as assembly factors, thermal margin, power density/layout, and cost. Figure 6 demonstrates the simulation results and illustrates how quick and easy it is to compare options that include both discrete and module-based MOSFETs.
Another example consists of a bidirectional, CLLC DC/DC on-board charging system running at 22 kW (which could be used for electric-vehicle charging applications). Because it would be used for EVs, the input voltage would vary widely at 380–900 VDC, while the output should provide 480–800 VDC. In this example, 3 output power levels are examined to estimate efficiency and junction temperature. The 3 outputs are 400V, 480V, and 610V all running at 36A output current. The topology selected is a full-bridge CLLC resonant converter operating at 135–250 kHz. The plan here is to run the simulation, check results, and then tweak as needed to optimize the design. This particular example can be seen in the reference design CRD-22DD12N.
For the first run on the input tab (see Figure 7), the user would enter input voltage, output voltage, output power, Lm/Lr, Fsw, and Fres. It’s best to start with Fsw = Fres (190 kHz). The rest can be auto-populated.
In the device tab, a 32-mΩ 1,200-V MOSFET is selected for both the primary and secondary sides to achieve high efficiency. Gate resistances are increased above the default setting, which results in increased switching losses but ensures design flexibility at the testing stage. Rg should be determined experimentally in circuit to achieve the desired voltage overshoot margin and electromagnetic interference performance.
For thermal properties, an isolated, liquid-cooled heatsink is chosen that maintains a maximum heatsink temperature of 65˚C. A high-performance aluminum nitride isolator with thermal grease on both sides will provide high isolation and low thermal resistance (the user guide shows 0.6 K/W) for the TO-247 solutions.
During simulation, the results of the first run show that the output power is too low. Because the basic principle of a CLLC converter states that lower operating frequencies boost output voltage (and output power), the simulation can be re-run with a lower switching frequency (reduced to 170 kHz). This improves the output power to an acceptable value and provides a usable solution (shown in Figure 8).
For this example, the user can compare results with several additional operating points by checking the “hold result” option, then return to the input tab and entering the new data. After re-simulating, adjust Fsw as necessary to tweak the desired output, and then repeat the process for the remaining operating points. This will output a summary of each result shown next to each other for comparison. This method can also be used to verify safe operating temperatures under all operating conditions.
Designers can benefit greatly from simulating a variety of configurations and homing in on optimized results. SpeedFit is an easy tool built on the PLECS platform that can replace days of manual datasheet comparisons and calculations. The designer stands to benefit greatly from finding suitable SiC MOSFETs and SiC diodes, estimating performance (and losses) at different operating points, determining thermal requirements of the system, assessing many different types of topologies, and capturing waveforms that can be used for capacitor and magnetic design.